Professor vid Institutionen för informationsteknologi, Datorteknik
I investigate modeling and measuring the effects of shared memory resources (caches and off-chip bandwidth) in multicore processors on power and performance. My work addresses both theoretical models and techniques for measuring actual behavior on real systems. Currently I am applying these techniques to improve task scheduling on heterogeneous systems, to predict power and performance, and to develop smart memory systems.
Nyckelord: computer architecture memory systems simulation runtimes scheduling
I received my PhD in Electrical Engineering from Stanford University in 2008. My research was in programming for real-time embedded processing on many-core processors in the Concurrent VLSI Architecture Group working with William Dally. After my PhD I worked at Apple on the development of the first OpenCL implementation for heterogeneous parallel processing across CPUs and GPUs, and then as a postdoc researcher in computer architecture in the Dept. of Information Technology at Uppsala University. I was appointed assistant professor in 2010 in the architecture research group at Uppsala looking at parallel programming systems and optimizations as part of the UPMARC research project. In 2014 I was promoted to Associate Professor (docent, lektor) and in 2017 to Professor. I was the Research Program Responsible Professor for the Computer Architecture and Communications Research Program from 2020 through 2022 and the Head of the Division of Computer Systems from 2022.
In addition to research, I led the ScalableLearning project (2012-2020) which brought the benefits of active, flipped-classroom teaching to nearly one hundred thousand students in Sweden and abroad. I was a co-founder of Green Cache AB (2014-2018), which developed and sold advanced memory systems technology. I also worked as the head of interactivity design at Collegial AB from 2018-2019.
Grants and Awards
- Wallenberg Academy Fellowship Prolongation (2020-2025)
- The Lilly and Sven Thurés prize (2020, The Royal Society of Sciences, Uppsala)
- Swedish Research Council (VR), Project Grant (2019-2023)
- Uppsala Technical Physics Students' Teaching Award (2019)
- European Research Council ERC Starting Grant (2017-2022)
- Uppsala University Pedaogical Prize (2016)
- Swedish Foundation for Strategic Research (SSF), Smart Systems Framework Grant (Co-PI, 2016-2021)
- Knut and Alice Wallenberg Foundation, Wallenberg Academy Fellow (2016-2021)
- Swedish Research Council (VR), Young Researcher Project Grant (2015-2018)
- Swedish Foundation for Strategic Research (SSF), Future Research Leaders (2013-2018)
- EU FP7, Addressing Energy in Parallel Technologies (Co-PI 2013-2016)
- Uppsala University, Pedagogical Development Grant for Flipped Classroom (2013)
- Swedish Research Council (VR), Framework Grant (Co-PI, 2012-2017)
- Uppsala Union of Engineering and Science Students, Teaching Award (2012)
- Stanford University, Centennial Teaching Assistant Award (2004)
- Stanford University, Hugh Hildreth Skilling Teaching Assistant Award (2003)
- Computer Architecture 1 (To view the interactive online course lectures, register at ScalableLearning and join with the enrollment key YRLRX-25436.)
- Parallel Programming for Efficiency (MSc level)
- Sample: Power and Energy in Computer Systems (52 min)
- Introduction to Computer Architecture Research (PhD level)
- Predicting Next-Generation Multicore Performance in a Fraction of a Second (Keynote, SICS Multicore Day, 2015)
- GPUs: The Hype, The Reality, and the Future (Keynote, SICS Multicore Day, 2013) PDF (2011)
- Flipped Classroom Teaching in an Introductory CS Course (KTH, 2013) PDF
- Resource Sharing in Multicore Processors (Keynote, Ericsson Software Research Day 2011)
- Introduction to OpenCL PDF
- Optimizing OpenCL PDF
- GPU Architectures for Non-Graphics People PDF
My research focuses on improving efficiency in computers by making the memory system more intelligent. Our work includes more clever ways of moving and placing data in the memory system, integrating data movement with the processor core itself, adapting runtime schedules for better data movement, and the analysis and modeling of data movement.
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